1. Field of the Invention
The present invention relates to a digital signal processor (DSP), and more specifically to a memory organization particularly well adapted to a DSP.
2. Discussion of the Related Art
FIG. 1 schematically and partially shows a conventional DSP architecture. The DSP includes four processing units operating in parallel. Two of these units are memory access units 10. An arithmetic unit 12 and a branch management unit 14 are further provided. Each of memory access units 10 is associated with an independent memory bus X or Y. A program memory 16 contains compound instructions INST, each compound instruction being actually formed of four simple instructions (INST1-INST4) provided at the same time to the respective units 10, 12, and 14. Of course, the four units are often not used at the same time. Then, the compound instruction provided by memory 16 includes NOPs corresponding to the unused units.
A DSP of the type of FIG. 1 is optimized to perform vector operations of the type x[i] OP y[j], where i and j vary, generally in a loop, and where OP designates any operation to be performed by arithmetic unit 12. Indeed, operands x[i] and y[i] can be fetched together via, respectively, bus X and bus Y and processed in the same cycle by arithmetic unit 12.
For this type of operation, values x[i] and values y[i] can be respectively stored in two independent memories respectively connected to buses X and Y.
However, a DSP may also need to perform operations of the type z[i] OP z[j], the values of z being all stored in a same memory. In this case, a value z, according to the unit 10 which receives the corresponding read instruction, may be fetched at one time by bus X, at another time by bus Y, or even by both buses at the same time. Thus, access should be possible to a same value z over both buses X and Y.
Theoretically, a dual port memory connected to buses X and Y may be used for this purpose. However, dual port memories are particularly costly in terms of surface.
FIG. 2 illustrates a memory organization which is preferred given the fact that the number of values submitted to operations of the type z[i] OP z[j] is relatively low. This organization includes a dual port memory 18, the size of which is sufficient to contain xe2x80x9czxe2x80x9d-type values, that is, the values which have to be accessible over both buses X and Y. Two single port memories 20 and 22 are respectively associated to xe2x80x9cxxe2x80x9d-type values and to xe2x80x9cyxe2x80x9d-type values, the xe2x80x9cxxe2x80x9d-type values being those which are only accessible over bus X and the xe2x80x9cyxe2x80x9d-type values being those only accessible over bus Y.
The first address bus of dual port memory 18 and the address bus of single port memory 20 are connected to address bus XA of memory bus X. Similarly, the second address bus of dual port memory 18 and the address bus of single port memory 22 are connected to address bus YA of memory bus Y. The first data bus of memory 18 and the data bus of memory 20 are routed to data bus XD of memory bus X via a multiplexer/demultiplexer 24. Similarly, the second data bus of memory 18 and the data bus of memory 22 are routed towards data bus YD of memory bus Y by a multiplexer/demultiplexer 26.
A decoder 28 controls multiplexers/demultiplexers 24 and 26 according to the addresses presented over buses XA and YA. In particular, when the address present on bus XA is in a specific range, decoder 28 controls multiplexer/demultiplexer 24 to route bus XD to memory 18. Outside the specific range, decoder 28 routes bus XD to memory 20. The same mechanism is used to control multiplexer/demultiplexer 26 according to the address present on bus YA.
Despite the complexity of multiplexers/demultiplexers 24 and 26, the surface occupied by this memory organization is generally smaller than that occupied by a single dual port memory gathering memories 18, 20, and 22, this given the fact that the capacity of dual port memory 18 is relatively low.
Multiplexers/demultiplexers 24 and 26 considerably increase the latency times of the read and write operations in the memories.
An object of the present invention is to provide a memory organization adapted to a digital signal processor enabling access to a same datum by two distinct channels while occupying a particularly small surface and not affecting the latency times of access to the data.
This and other objects are achieved by means of a data processing system comprising a processor provided with two memory access units operating in parallel; two separate memories respectively associated with the two access units; and means for, when the address of a datum to be written into a memory is in a predetermined address range, writing the datum into both memories at the same time at the same address.
According to an embodiment of the present invention, said means comprise two identical write instructions provided at the same time to the two access units.
According to an embodiment of the present invention, said means comprise a first multiplexer connected to copy, in a first access unit a write instruction provided to the second access unit when the write address is in the predetermined range.
According to an embodiment of the present invention, said means comprise a second multiplexer connected to copy into the second access unit a write instruction provided to the first access unit when the write address is in the predetermined range.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.